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Property:tc (cpuinfo)
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Name-Collision - multiple objects in this wiki use the name tc!
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CPUinfo-Property
| Property: | tc (cpuinfo) - type CPUinfo | Wiki | Freetz | IPPF | whmf | AVM | Web |
| Location: | Box-Models >> Benchmark-Results - Origin: MIPS | ||||||
| Value: | 0, 1 | ||||||
| Properties: | Firmware: 6.87 | ||||||
| Function: | MIPS: Thread Context of the physical core running the vpe running this logical processor | ||||||
Goto: Examples - Dependencies - Model-Matrix - Help Supportdata2 - SMW-Browser
Details
TC lists the Thread Context (TC) of the physical core running the vpe running this logical processor of the MIPS.
On MIPS with mt support in ases-implemented each physical core has 2 vpes.
A vpe could be seen as a hyperthreading core.
Additionally there are 9 TCs, which can be allocated across the two vpes each core.
A TC is a “lighter weigh" concept of multithreading, but provides an own execution environment.
The VR9 in the 7412 has 1 physical core with 2 VPEs running 2 processors:
On other VR9 models the vpe concept is enough to run 2 processors.
Adding the TC concept seems superfluous at the first view.
But this enables allocating up to 7 further TCs across both vpes without disturbing the processors.
This is likely done to run audio codecs with the dsp ases-implemented on an own TC.
Other models use a vpefw. The 7412 has an own TC based concept.
Examples
MIPS cpuinfo - Excerpt from the 7590ax fw 7.39 - the Options implemented and mips-options are just single lines:
system type : GRX500 rev 1.2 # global per device block machine : AVM7590ax (GRX550, HW259) Main model # this empty line is missing processor : 0 # first per processor block cpu model : MIPS interAptiv (multi) V2.0 BogoMIPS : 239.24 wait instruction : yes microsecond timers : yes tlb_entries : 32 extra interrupt vector : yes hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb] isa : mips1 mips2 mips32r1 mips32r2 ASEs implemented : dsp mt eva Options implemented : tlb tlbinv segments 4kex 4k_cache prefetch mcheck ejtag llsc pindexed_dcache userlocal vint perf_cntr_intr_bit cdmm nan_legacy nan_2008 ebase_wg perf shadow register sets : 1 kscratch registers : 0 package : 0 core : 0 VPE : 0 TC : 0 # added from 7412 VCED exceptions : not available VCEI exceptions : not available mips-options: 0x006d638b icache.flags 0x00000000 # added from VR9 dcache.flags 0x00000004 isa_level 0x00000063 ases 00000031 processor : 1 # second per processor block <snip>
Dependencies
Daily updated index of all dependencies of this property. Last update: GMT.
A ** in the Mod column marks info from Supportdata2 probes, which will always stay incomplete.
A - in the Mod column marks manual research, the Firmware then shows where the Object occurs, not the Relation.
| Relation | Typ | Object | Mod | Firmware | Info | Origin |
|---|---|---|---|---|---|---|
| 0 dependencies for this property | ||||||
Model-Matrix
Daily updated index of the presence, path and size of this property for each model. Last update: 2024-12-23 05:10 GMT.
Showing all models using this property. Click any column header (click-wait-click) to sort the list by the respective data.
The (main/scrpn/boot/arm/prx/atom/rtl) label in the Model column shows which CPU is meant for Multi-Linux models.
Note that this list comes from Supportdata2 probes, which can have arbitrary settings and come from different firmware versions.
It doesn't say much if a model is not listed here. It may be a missing supportdata2 file or just a disabled feature.
| Model | Firmware | Value | SoC |
|---|---|---|---|
| FRITZ!Box 7412 | 6.87 | 0, 1 | VR9 |
| 1 model uses this property | |||
Help Supportdata2
The data in this article is incomplete since it was manually collected using the Supportdata2 project.
Unlike the Supportdata-Probes which have been collected for years Supportdata2 is brand new and only has a few probes.
If you have access to a shell then please help to extend the Supportdata2 collection to improve this data.
It's easy and it's done in minutes. Please send created data as an Email attachment to the address listed here. Thanks!
